If I remember correctly there are three options to select from the SDF. To be on the safe side you have to run all of them.
Gate-level simulation runs very slow so this might be a tedious task.
I did for an FPGA project, (FPGA SDF files sometimes have all the three options the same) :
"The net-list and SDF are generated using netgen command:
netgen -sim -ofmt vhdl test.ncd
Two files are generated: test.vhd and test.sdf...."
Thanks, pini_1.
What do you mean about "To be on the safe side you have to run all of them" ?
Shall we run the mixed mode, like max delay on data path, and min delay on clock path ?
Thanks!