How to do formal check after clock gate clone ?

[owen_li]

Hi.

Coz I need to some stubborn clock gating setup violation, I made some clock gating cell clone.
My question is how to do formak check then.
Is there extra setting needed to be set in formal tool ? thanks!

 

[layowblue]

as long as the cloning is "identical" to the original one despite the routing, formal tool should be able to either merge it or regard cloning cells as equivalent to the golden design.