Why would it have to have 40 states? You can have one state that counts to 40, and upon reaching 40, it goes to the next state where your signal is set to one, and it stays in that state until the block is reset, or some other condition of your choosing.
Having said that, you just need to have a counter that counts up to 40 and then stops. When the counter is less than 40, your signal is zero, and when it is equal to 40, it is one.
entity count_40 id
port( clk,reset :in std_logic;
op ut std_logic;
);
end count_40;
architecture arch_count_40 of count_40 is
signal count:integer(0 to 41);
begin
process(clk,reset)
begin
if (reset= '0') then
count<= 0;
elsif(clk'event and clk='1')
count<= count+'1';
else count<= '41';
end process;
prathiba's code will work, but not written in a efficient way, I just wrote it in FSM approach and here the counter will not toggle all the time while clock is running.
case(state)
reset :
next_state = count;
count :
begin
if(count_number != count_num_param)
begin
next_state = count;
next_count_number = count_number + 1;
end
else
begin
next_state = no_count;
next_count_number = 0;
end
end
no_count :
next_state = no_count;
endcase
end
always@(posedge reset or posedge clock)
if(reset) begin
state <= reset;
count_number <= 0;
end
else begin
state <= next_state;
count_number <= next_count_number;
end
architecture rtl of count40 is
signal count : std_logic_vector(41 downto 0);
signal hit40 : std_logic;
begin
process(clk,rstn)
begin
if (rstn = '0') then
count <= (others => '0');
hit40 <= '0';
elsif(clk'event and clk='1')
if (unsigned(count) <= 41) then
count <= count + '1';
else
-- once we get here hit40 stays '1' and counter stops
hit40 <= '1';
end if;
end process;
end rtl;