jiang
Advanced Member level 4

rtl compiler virtual directory
Hi All,
My customer use Synopsys gtech gate level netlist verilog format
as hand-off format. (set target_library = gtech.db in DC)
But we use Cadence RTL compiler as synthesis tool.
How to compile Synopsys gtech gate netlist in RTL compiler to otimize
and map to technology library cells?
Hi All,
My customer use Synopsys gtech gate level netlist verilog format
as hand-off format. (set target_library = gtech.db in DC)
But we use Cadence RTL compiler as synthesis tool.
How to compile Synopsys gtech gate netlist in RTL compiler to otimize
and map to technology library cells?