Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

How to do cell mapping in RTL compiler

Status
Not open for further replies.

jiang

Advanced Member level 4
Joined
Dec 31, 1999
Messages
111
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,296
Location
Taiwan
Activity points
855
rtl compiler virtual directory

Hi All,

My customer use Synopsys gtech gate level netlist verilog format
as hand-off format. (set target_library = gtech.db in DC)
But we use Cadence RTL compiler as synthesis tool.
How to compile Synopsys gtech gate netlist in RTL compiler to otimize
and map to technology library cells?
 

aravind

Advanced Member level 1
Joined
Jun 29, 2004
Messages
487
Helped
45
Reputation
94
Reaction score
18
Trophy points
1,298
Location
india
Activity points
3,597
what does rtl compiler do ?

RTL compiler having GTech library incide /hdl_libraries
u can run synopsys netlist no problem will occur.
load_hdl RTL_PATH/*v
elab
techmap

run this commands
if u face any problem send the error message i will try to debug it
 

jiang

Advanced Member level 4
Joined
Dec 31, 1999
Messages
111
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,296
Location
Taiwan
Activity points
855
rtl compiler

aravind said:
RTL compiler having GTech library incide /hdl_libraries
u can run synopsys netlist no problem will occur.
load_hdl RTL_PATH/*v
elab
techmap

run this commands
if u face any problem send the error message i will try to debug it
I don't find hdl_libraries directory and RTL compiler seems not to support thes commands your provided.
I only find gtech.alf.
 

omara007

Advanced Member level 4
Joined
Jan 6, 2003
Messages
1,238
Helped
50
Reputation
102
Reaction score
16
Trophy points
1,318
Location
Cairo/Egypt
Activity points
9,747
synopsys gtech library mapping

Does RTL Compiler read synopsys technology file (.db) or just (.lib) ?
 

joe2moon

Full Member level 5
Joined
Apr 19, 2002
Messages
280
Helped
19
Reputation
38
Reaction score
7
Trophy points
1,298
Location
MOON
Activity points
3,749
rtl compiler cadence [map-2] [synthesize]

hdl_libraries/
-- This is RC's virtual directory, not a directory under tool installation dir.

-- You can see this directory after you invoke rc, and type ls
rc> ls
rc:/> ls
./ designs/ hdl_libraries/ libraries/ messages/


-- Furthermore, you can browse the content of this virtual directory
rc:/> cd /hdl_libraries/

rc:/hdl_libraries> ls
 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top