how to divide 40MHZ clock pulse to 44.24 KHZ and 18 KHZ

[danielkonduru]

please help me how to divide clock
iam using vhdl in fpga
and by using dcm's is better or not and how to use dcm's
please help me

thanks.

 

[syedshan]

hmm.. If you are using any of the Xilinx FPGA before Virtex 6 (i.e. spartan 3 or Virtex 5 etc.) then DCM is the best option for dividing clock.
Well I use Virtex 6 and in that clocking wizard does the job so I dont know much how to use DCM, only that it is easy to use, using the Core Generator, you will create the core for your appropriate clock and then instantiate it into your design.

You can find great help for this just google it. btw what FPGA are you using?

 

[FvM]

When working with Xilinx FPGAs, it's a good idea to review Xilinx documents (user guides, application notes) when referring to specific features, e.g. DCM.

In a more general view, you should consider how exact the said clock frequencies can be met, respectively what you require. You'll notice that 18 kHz frequency can be achieved exactly, when using x9 PLL frequency multiplication (a more complex function than basic DCM) and 44.24 kHz can't be met exactly. You have to accept either a frequency deviation or some jitter with a fractional divider. Because you didn't tell any performance requirements, I won't elaborate on possible solutions. They are general knowledge in the FPGA world anyway, I suppose.

 

[BlackHelicopter]

In a more general view, you should consider how exact the said clock frequencies can be met, respectively what you require. You'll notice that 18 kHz frequency can be achieved exactly, when using x9 PLL frequency multiplication (a more complex function than basic DCM)

I was reading through application notes for various FPGAs and there seems to be a minimum frequency specified for the DCM's and PLL's usually around a couple MHz (sometimes in the hundreds of kHz, depending on the device). Generating an 18kHz frequency from an internal PLL doesn't appear feasible. Is there a workaround?

 

[RCinFLA]

You might stop thinking of them as dividers and start thinking of period counters. A 40 MHz signal has a period of 25 nsecs. This is your minmum increment for a waveform of any derived frequency for a direct counter (divider) scheme. (You can use half cycle periods but duty cycle becomes critical).

44.24 KHz has a period of 22.603978 usecs. Dividing this by 25 nsecs does not yield an integer. (904.15913) No combination of sequenced direct dividers will get you there.

You need a PLL to go up in freq to a common divisible number to 44.24 KHz.

DCM's use DLL (delay locked loop) which is a PLL that uses a ring oscillator VCO to generate controlled precise phase shift taps on the VCO. It can then pick sequences of taps to create non-integer based frequencies.

 

[FvM]

Generating an 18kHz frequency from an internal PLL doesn't appear feasible. Is there a workaround?

There's no actual requirement to generate the low frequencies by the PLL directly. A postdivider in the regular FPGA fabric can be cascaded with the PLL. The purpose of the PLL is to generate a multiple of the input clock to get the output frequency by a pure integer division. As said, this works at least for 18 kHz.

The problem is however that no exact requirements for the two low frequency clocks have been told. It's rather easy to derive both frequencies by a DDS generator from the 40 MHz input clock. But the DDS output is time discrete, involving a certain amount of jitter. It's unclear, if it can be accepted for this application.

 

[danielkonduru]

thank you all.
how to instantiate dcm's in spartan3e fpga using vhdl

 

[syedshan]

Ok.

If you have been able to generate the ip core for the DCM then it is quite simple to instantiate, just click on the IPcore icon in the Design pane then double click on 'View HDL Functional Model' in the Process menu and copy paste the Instantiation code