higildedzest
Junior Member level 3
how i can divide 32768hz clock signal to 1hz clock signal? i have written the code.but it is diffcult to see the simulation result.who can give me a good advice ,thank you.
Follow along with the video below to see how to install our site as a web app on your home screen.
Note: This feature may not be available in some browsers.
module DIVIDER(clkin,reset,clkout,count);
input clkin,reset;
output clkout,count;
reg clkout;
reg [15:0] count;
always @(posedge clkin)
begin
if (reset)
begin
count<=0;
clkout<=clkout;
end else
begin
if(count==32767)
begin
count<=0;
clkout<=clkout;
end
else if(count<32767)
begin
count<=count+1;
clkout<=count[15];
end
end
end
endmodule
this is my code.i can not get the simulation waveform clearly.
module top (clk, out);
input clk;
reg [14:0] count = 0;
output out;
assign out = count[14];
always @ (posedge clk)
count <= count + 1;
endmodule
module top (clk, out);
input clk;
reg [14:0] count = 0;
output reg out = 0;
always @ (posedge clk) begin
count <= count + 1;
out <= count == 32767;
end
endmodule
hi,dmk said:Well, the ech047 said what I had to say.
I don't use Verilog, but in VHDL it looks quite the same.