how i can divide 32768hz clock signal to 1hz clock signal? i have written the code.but it is diffcult to see the simulation result.who can give me a good advice ,thank you.
hi,
what you said is right,but how can i see the whole simulation waveform?
Code:
module DIVIDER(clkin,reset,clkout,count);
input clkin,reset;
output clkout,count;
reg clkout;
reg [15:0] count;
always @(posedge clkin)
begin
if (reset)
begin
count<=0;
clkout<=clkout;
end else
begin
if(count==32767)
begin
count<=0;
clkout<=clkout;
end
else if(count<32767)
begin
count<=count+1;
clkout<=count[15];
end
end
end
endmodule
this is my code.i can not get the simulation waveform clearly.