yuenkit
Advanced Member level 4
virsim
hi,
I know how to use DVE to display MDA.
I am just wondering how to do that in Virsim.
I am using vcs 2005.06
I manage to display in Virsim, but I dont think this is the proper way.
first, I include $vcdplusmemon in verilog.
the i run "vcs -RI mem_test.v""
when Virsim open, I open Hierarchy and Logic window.
I drag the design to Logic window. The MDA variable still havent shown yet.
Then i run 1 time step. and I click on th input of the MDA block in logic window.
But the Hierachy window shows 2 MDA variable, which have the same name.
This is the way i discovered. If you know the correct way, please let me know. Thanks.
hi,
I know how to use DVE to display MDA.
I am just wondering how to do that in Virsim.
I am using vcs 2005.06
I manage to display in Virsim, but I dont think this is the proper way.
first, I include $vcdplusmemon in verilog.
the i run "vcs -RI mem_test.v""
when Virsim open, I open Hierarchy and Logic window.
I drag the design to Logic window. The MDA variable still havent shown yet.
Then i run 1 time step. and I click on th input of the MDA block in logic window.
But the Hierachy window shows 2 MDA variable, which have the same name.
This is the way i discovered. If you know the correct way, please let me know. Thanks.