asynchronous reset
A related topic ...
If your design doesn't absolutely require an external reset input, and if you simply want to ensure that your registers start-up in predefined states, then I suggest using your device's built-in features (if available) for presetting the registers. That's usually easy to do in modern FPGAs and CPLDs: when you declare a register in HDL, simply specify its initial value. Eliminating the reset net could simplify the routing and speed up your design, especially if you are eliminating synchronous reset.
Some devices, such as old GALs and PLDs, don't provide any automatic preset mechanism.
If you really do need to respond to the reset signal from the PC, then disregard the above stuff.
By the way, if you apply an asynchronous reset to clocked synchronous logic, then you must take precautions to avoid violating the reset-to-clock timing requirements of the flops.