How to differentiate between synchronous and asynchronous resets?

[Harinadhan]

hai,
i designed a system , which get reset from the parallel port of pc........
which is asynchronous. But i sampled it with the faster clock in the design. Do u
think that now this reset is synchronous. How can we differentiate syn and asyn resets.
please help me...........

 

[banjo]

asynchronous reset

Once you sample the reset input with an internal FPGA clock, then the reset pulse is syncronized with the clock. When you apply this reset to flip-flops within the FPGA, it depends on your coding as to whether the compiler will use async or sync resets on the flops. The following syntax gives async resets in Verilog:

always @ (posedge vliw_clk or posedge mst_rst)
begin
if (mst_rst)
ebwe_dly_1q <= 'd0;
else
ebwe_dly_1q <= ebwe_dlyd_e;
end

Notice that transitions of either signal causes a change in the flop because both are listed in the sensitivity statement.

For sync resets, the sensitivity statement must only include the clock.

always @ (posedge vliw_clk )
begin
if (mst_rst)
ebwe_dly_1q <= 'd0;
else
ebwe_dly_1q <= ebwe_dlyd_e;
end

Only in special cases do you really need to worry about whether the reset was sync or async. If your clock is gated by another signal and you want to insure that a flop is in a particular state BEFORE the next clock edge, then async is required.
If you just want to insure the flop's state after power-up, the either type will work.

 

[echo47]

asynchronous reset

A related topic ...

If your design doesn't absolutely require an external reset input, and if you simply want to ensure that your registers start-up in predefined states, then I suggest using your device's built-in features (if available) for presetting the registers. That's usually easy to do in modern FPGAs and CPLDs: when you declare a register in HDL, simply specify its initial value. Eliminating the reset net could simplify the routing and speed up your design, especially if you are eliminating synchronous reset.

Some devices, such as old GALs and PLDs, don't provide any automatic preset mechanism.

If you really do need to respond to the reset signal from the PC, then disregard the above stuff.


By the way, if you apply an asynchronous reset to clocked synchronous logic, then you must take precautions to avoid violating the reset-to-clock timing requirements of the flops.

 

[satishkumar]

asynchronous reset

HI,

SOME TIMES IF U GIVE ASY ALSO IT TURN TO SYN

IT IS TRUE