How to determine fpga resource usage per component and per process

matrixofdynamism said:

When we compile project in Altera Quartus ii, at the end we get resource usage. This gives total usage of logic elements, dsp slices and memory bits.

Is it possible to find how many fpga resources were used per component instance in design hierarchy and also per process?

Click to expand...

also per process

Click to expand...

matrixofdynamism said:

I hope I can use it to simplify the design if I can find some inefficiencies

Click to expand...

Looking at resource usage per entity isnt really going to tell you if something is written inefficiently. It just tells you if a specific block is a specific size. The synth has created a circuit for you that implements your code, so determining if something is "efficient" is more a design/architecture/code problem rather than something you'll determine from the fit report.

Click to expand...