How to detect that signal changed at posedge clk?

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KingMoshe

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Hello,
I have an input signal that can be initiate at "0" or "1".
I want to detect if the signal changed from "0" to "1" or from "1" to "0" @ posedge clock

How can I do it?

I tried:
Always @ (posedge clk) begin
if (~input_signal)
xxx = 1'b0;
end
 

Try
Code:
always @ (posedge clk) begin
input_v <= input_signal;
if (input_signal^input_v)
xxx <= 1'b0;
end
 

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