Mar 21, 2022 #1 K KingMoshe Member level 2 Joined Aug 10, 2021 Messages 48 Helped 0 Reputation 0 Reaction score 0 Trophy points 6 Activity points 362 Hello, I have an input signal that can be initiate at "0" or "1". I want to detect if the signal changed from "0" to "1" or from "1" to "0" @ posedge clock How can I do it? I tried: Always @ (posedge clk) begin if (~input_signal) xxx = 1'b0; end
Hello, I have an input signal that can be initiate at "0" or "1". I want to detect if the signal changed from "0" to "1" or from "1" to "0" @ posedge clock How can I do it? I tried: Always @ (posedge clk) begin if (~input_signal) xxx = 1'b0; end
Mar 21, 2022 #2 FvM Super Moderator Staff member Joined Jan 22, 2008 Messages 52,472 Helped 14,756 Reputation 29,794 Reaction score 14,119 Trophy points 1,393 Location Bochum, Germany Activity points 298,318 Try Code: always @ (posedge clk) begin input_v <= input_signal; if (input_signal^input_v) xxx <= 1'b0; end Upvote 0 Downvote
Try Code: always @ (posedge clk) begin input_v <= input_signal; if (input_signal^input_v) xxx <= 1'b0; end
Mar 22, 2022 #3 dpaul Advanced Member level 5 Joined Jan 16, 2008 Messages 1,802 Helped 317 Reputation 635 Reaction score 343 Trophy points 1,373 Location Germany Activity points 13,096 @KingMoshe Google "rising edge detection VHDL" or "falling edge detection VHDL" -- thousands of code examples are there! Upvote 0 Downvote
@KingMoshe Google "rising edge detection VHDL" or "falling edge detection VHDL" -- thousands of code examples are there!