[SOLVED] how to detect a pulse which is 1/10th of receiving clock

[rajaraman]

Hi all,
I have a block which is working at 100 Mhz . An input which is 1/10th of 100 mhz oulse.How can i detect that.Kindly help me out in this.

 

[FvM]

Basically by a combination of synchronous registers and asynchronous load. See the below VHDL hardware description:

process (pulse_in,clk)
  begin
    IF pulse_in = '1' THEN
      pulse_latch <= '1';
    ELSIF RISING_EDGE(clk) THEN
      pulse_latch <= '0';
    END IF;
    IF RISING_EDGE(clk) THEN
      pulse_out <= pulse_latch;
    END IF;
  end process;

P.S.: In your case, if the hardware isn't fast enough to react on a 1 ns pulse, it doesn't work. For fast pulses, an alternative solution is to clock a register by pulse_in and perform an asynchronous reset on the acknowledge from system clock domain.

process (pulse_in,clk)
  begin
    IF pulse_out = '1' THEN
      pulse_latch <= '0';
    ELSIF RISING_EDGE(pulse_in) THEN
      pulse_latch <= '1';
    END IF;
  end process;

process (clk)
  begin
    IF RISING_EDGE(clk) THEN
      pulse_out <= pulse_latch;
    END IF;
  end process;

 

[lostinxlation]

You have to latch the event by the input data.
Only requirement is that the input data width meets the minimum pulse of the latch.

Verilog code would be something like this. This is just off the top of my head, so refine the details yourself.

always @(in or sync_s2 or rst_n) begin
  if(!rst_n) latch <= 0;
  else if(sync_s2) latch <= 0;
  else if(in) latch <= 1;
end

always @(posedge clk100mhz or negedge rst_n) begin
   if(!rst_n) {sync_s1, sync_s2} <= 2'b0;
   else 
   {sync_s2, sync_s1} <= {sync_s1, latch};
end

assign use_this_in_100MHz_domain = sync_s2;

 

[skyfaye]

One commonly used method is to stretched the high frequency pulse and then sync it to the low frequency's clock domain. I'm assuming your 2 clocks are generated by different source and is considered to be in different clock domains. If not, then you don't need the synchronizer.

//
// stretcher
//
always @ (posedge hi_clk)
begin
if (hi_reset) begin
din_reg_0 <= #1 1'b0;
din_reg_1 <= #1 1'b0;
din_reg_2 <= #1 1'b0;
strch_pulse <= #1 1'b0;
end
else begin
din_reg_0 <= #1 pulse_in;
din_reg_1 <= #1 din_reg_0;
din_reg_2 <= #1 din_reg_1;
strch_pulse <= #1 din_reg_0 | din_reg_1 | din_reg_2; // add more stages to stretch it to wider than the low frequency clock period
end
end

//
// sync to the stretched pulse to the low frequency clock domain
//
reg sync_ff_0, sync_ff_1;
always @ (posedge lo_clk)
begin
sync_ff_0 <= #1 strch_pulse;
sync_ff_1 <= #1 sync_ff_0;
end

- Hung