wjx197733
Member level 2
Hi all, I am a fresh man to design analog circuit.
These days I design a simple OP, as you can see in the attachment. The main parameter of the OP is:
VDD=5V, SR>=10V/µs (CL=5pF), f-3dB>=100kHz (CL=5pF), a small signal gain of 100V/V, 1V<=ICMR<=4.5V, and Pdiss<=1mW. Use the parameters of KN’=110µA/V2, KP’=50µA/V2, VTN=0.7V, VTP=-0.7V,
λN=0.04V-1 and λP=0.05V-1.
The w/l of most MOS has been confirmed, but confirm the w/l of M8 is so difficult for me. if I replace M8 by a current socrce, there have no problem, so I think the w/l of most MOS is rignt.
How to design the w/l of M8? help me please!!!
These days I design a simple OP, as you can see in the attachment. The main parameter of the OP is:
VDD=5V, SR>=10V/µs (CL=5pF), f-3dB>=100kHz (CL=5pF), a small signal gain of 100V/V, 1V<=ICMR<=4.5V, and Pdiss<=1mW. Use the parameters of KN’=110µA/V2, KP’=50µA/V2, VTN=0.7V, VTP=-0.7V,
λN=0.04V-1 and λP=0.05V-1.
The w/l of most MOS has been confirmed, but confirm the w/l of M8 is so difficult for me. if I replace M8 by a current socrce, there have no problem, so I think the w/l of most MOS is rignt.
How to design the w/l of M8? help me please!!!