Apr 7, 2015 #1 E EHY Member level 1 Joined Apr 2, 2015 Messages 36 Helped 0 Reputation 0 Reaction score 0 Trophy points 6 Activity points 235 As i attach the image, I want to design the circuit like SR-latch but quite different. If the rising edge of S signal is high, output Q is high(set) Otherwise, if the rising edge of R signal is high, output Q is low(reset). output Q of conventional SR-latch using nor gates is low when S and R is high (S=1,R=1) I don't want this operation. I just want circuit. the rising edge of S and R controls output signal Q. plz help me`~
As i attach the image, I want to design the circuit like SR-latch but quite different. If the rising edge of S signal is high, output Q is high(set) Otherwise, if the rising edge of R signal is high, output Q is low(reset). output Q of conventional SR-latch using nor gates is low when S and R is high (S=1,R=1) I don't want this operation. I just want circuit. the rising edge of S and R controls output signal Q. plz help me`~
Apr 7, 2015 #2 KlausST Advanced Member level 7 Joined Apr 17, 2014 Messages 25,180 Helped 4,868 Reputation 9,757 Reaction score 5,544 Trophy points 1,393 Activity points 168,474 Hi, Instead of using fli flops you could use combinatorial solution: Q = C AND !R Two resistors and a bjt is sufficient Klaus
Hi, Instead of using fli flops you could use combinatorial solution: Q = C AND !R Two resistors and a bjt is sufficient Klaus
Apr 9, 2015 #3 E EHY Member level 1 Joined Apr 2, 2015 Messages 36 Helped 0 Reputation 0 Reaction score 0 Trophy points 6 Activity points 235 KlausST said: Hi, Instead of using fli flops you could use combinatorial solution: Q = C AND !R Two resistors and a bjt is sufficient Klaus Click to expand... Thank you but, What is solution using Flip Fliops?
KlausST said: Hi, Instead of using fli flops you could use combinatorial solution: Q = C AND !R Two resistors and a bjt is sufficient Klaus Click to expand... Thank you but, What is solution using Flip Fliops?
Apr 9, 2015 #4 E EHY Member level 1 Joined Apr 2, 2015 Messages 36 Helped 0 Reputation 0 Reaction score 0 Trophy points 6 Activity points 235 How to design the following operation?? I want to design circuit when the rising edge of signal S is triggered, then output Q is high(set) and when the rising edge of Signal R is triggred, then output Q is low(reset) (edge triggered SR-flip flop ?!) I don't want combinational logic , Q=S and ~R plz help me~
How to design the following operation?? I want to design circuit when the rising edge of signal S is triggered, then output Q is high(set) and when the rising edge of Signal R is triggred, then output Q is low(reset) (edge triggered SR-flip flop ?!) I don't want combinational logic , Q=S and ~R plz help me~
Apr 9, 2015 #5 D.A.(Tony)Stewart Advanced Member level 7 Joined Sep 26, 2007 Messages 9,013 Helped 1,824 Reputation 3,647 Reaction score 2,202 Trophy points 1,413 Location Richmond Hill, ON, Canada Activity points 59,600 Re: How to design the following operation?? The edge triggered Flip Flop may be designed using gates is also called a Type II Phase Detector. Either it is level sensitive or edge sensitive. It is impossible to do without Logic. What are your real constraints?
Re: How to design the following operation?? The edge triggered Flip Flop may be designed using gates is also called a Type II Phase Detector. Either it is level sensitive or edge sensitive. It is impossible to do without Logic. What are your real constraints?
Apr 9, 2015 #6 E EHY Member level 1 Joined Apr 2, 2015 Messages 36 Helped 0 Reputation 0 Reaction score 0 Trophy points 6 Activity points 235 Re: How to design the following operation?? SunnySkyguy said: The edge triggered Flip Flop may be designed using gates is also called a Type II Phase Detector. Either it is level sensitive or edge sensitive. It is impossible to do without Logic. What are your real constraints? Click to expand... i want operation of the attached image
Re: How to design the following operation?? SunnySkyguy said: The edge triggered Flip Flop may be designed using gates is also called a Type II Phase Detector. Either it is level sensitive or edge sensitive. It is impossible to do without Logic. What are your real constraints? Click to expand... i want operation of the attached image
Apr 9, 2015 #7 D.A.(Tony)Stewart Advanced Member level 7 Joined Sep 26, 2007 Messages 9,013 Helped 1,824 Reputation 3,647 Reaction score 2,202 Trophy points 1,413 Location Richmond Hill, ON, Canada Activity points 59,600 Re: How to design the following operation?? What about if R precedes S?
Apr 9, 2015 #8 KlausST Advanced Member level 7 Joined Apr 17, 2014 Messages 25,180 Helped 4,868 Reputation 9,757 Reaction score 5,544 Trophy points 1,393 Activity points 168,474 Re: How to design the following operation?? Hi, i can´t imagine a dual clock triggered flipflop. What´s wrong with the combinatorial solution? Is it too easy? Klaus
Re: How to design the following operation?? Hi, i can´t imagine a dual clock triggered flipflop. What´s wrong with the combinatorial solution? Is it too easy? Klaus
Apr 9, 2015 #9 E EHY Member level 1 Joined Apr 2, 2015 Messages 36 Helped 0 Reputation 0 Reaction score 0 Trophy points 6 Activity points 235 Re: How to design the following operation?? KlausST said: Hi, i can´t imagine a dual clock triggered flipflop. What´s wrong with the combinatorial solution? Is it too easy? Klaus Click to expand... because simple cmos gate logic has process speed limitation so i have to implement such CML type circuit - - - Updated - - - SunnySkyguy said: What about if R precedes S? Click to expand... If rising edge of R signal is trigerred firstly, the output Q is just low and then if rising edge of signal S is trigerred , the output Q is high
Re: How to design the following operation?? KlausST said: Hi, i can´t imagine a dual clock triggered flipflop. What´s wrong with the combinatorial solution? Is it too easy? Klaus Click to expand... because simple cmos gate logic has process speed limitation so i have to implement such CML type circuit - - - Updated - - - SunnySkyguy said: What about if R precedes S? Click to expand... If rising edge of R signal is trigerred firstly, the output Q is just low and then if rising edge of signal S is trigerred , the output Q is high