How to design the sub-block's on-chip test mode???

[firry]

hello
i am a newbie in the design of test mode , i want a tutorial that has fundamentals and concepts of how to design on-chip test mode in a good manner i.e. general rule and constraints ..etc....note that i dont mean the roles that depend on the technology ,,i mean general ones,,,,,,thanks

 

[mask_layout]

Hi, I may be an idiot here.. But what is "on-chip" test mode... Does it have anything to do with layout or it is on the simulation part?

 

[firry]

Hi, I may be an idiot here.. But what is "on-chip" test mode... Does it have anything to do with layout or it is on the simulation part?

the ciruit of test mode and the fuction circuit(sub-block of chips) will be simulated and fabricated together. the difference between them is their work condition. the test mode is part of the hole chip.