Hello guys,
I'm confused about how to decide the parameters of PLL(loop bandwidth, phase margin etc.)
I know the loop bandwidth should smaller than 0.1*phase detect frequency so that the system is stable.
And there is always a trade off between lock time and phase noise/spur.
However, is there any way to design the loop bandwidth to be a specific value?(If I only care about the phase noise and jitter)
Or the value have to be decided by the rule of thumb and trial and error?