How to design the parameter of PLL?

[s82223]

Hello guys,

I'm confused about how to decide the parameters of PLL(loop bandwidth, phase margin etc.)

I know the loop bandwidth should smaller than 0.1*phase detect frequency so that the system is stable.

And there is always a trade off between lock time and phase noise/spur.

However, is there any way to design the loop bandwidth to be a specific value?(If I only care about the phase noise and jitter)

Or the value have to be decided by the rule of thumb and trial and error?

 

[BigBoss]

There isn't such rule as "loop bandwidth should be smaller than.." It depends on many parameters.
Phase noise has also many contributors and there is only one trade-off between locking time and loop bandwidth.
I suggest you to read more about PLL systems and find-if it's available- working examples and work on them..

 

[D.A.(Tony)Stewart]

What are you specs for jitter, lockup time and max f err? and "type" of mixer

normally filter has lead/lag compensation to speed up locktime.

 

[s82223]

What are you specs for jitter, lockup time and max f err? and "type" of mixer

normally filter has lead/lag compensation to speed up locktime.

I don't have these specs when designing PLL.

All I know is that I have to minimize the jitter while the phase noise doesn't perform too bad.

I saw a design metric from "PLL performance, Simulation and Design" which said that if I want to optimize the jitter performance, the best choice is to find the cross point of VCO phase noise and PLL phase noise.

However, is it possible to measure only PLL noise?