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If I understand your question correctly, you want to design a chip which is meeting EMI (electromagnetic interface) standards, if so,
1. Ensure the chip has less Power Grid noise.
2. Ensure the high switching pads placed in the center of the chip so that the leads which connects from the pads are lesser which in-turn causes lesser EMI noise issues.
3. Ensure that you meet your SSN(simultaneous switching noise) standards , which in-turn will help to meet your EMI requirements.