Re: design pipelined ADC
Hi.
As you know, error and noise of this last stage will be divided by the whole gain of previous stages to have the input-referred error or noise. Hence, its design would be very relax. Conventionally we assume that this stage contains no error at all. But if this assumption does not hold true, there would be an error in LSB of the final output number and total SNDR won't be degraded dramatically. This is the main reason that nobody talks about the methodology of last stage design.
Regards,
EZT