No It is not possible to 'design' an adc or dac using vhdl/verilog.
However it is possible to 'model' an adc or dac using vhdl/verilog
You dont HAVE to use ams if you dont want to. Simple ADC and DAC can be modelled using simple vhdl/verilog
hope it helps,
Kr,
Avi http://www.vlsiip.com