How to design DAC and ADC using Verilog/VHDL?

[rajakash]

hi friends

is it possible to design DAC and ADC using verilog or vhdl..
pls
i have this doubt ..help me

 

[echo47]

adc and dac

No, Verilog and VHDL don't support analog.

Instead, you could use Verilog-AMS or VHDL-AMS.

 

[avimit]

Re: adc and dac

No It is not possible to 'design' an adc or dac using vhdl/verilog.
However it is possible to 'model' an adc or dac using vhdl/verilog
You dont HAVE to use ams if you dont want to. Simple ADC and DAC can be modelled using simple vhdl/verilog
hope it helps,
Kr,
Avi
http://www.vlsiip.com

 

[ameed]

Re: adc and dac

hi,
yes we can design and if have code then see on opencores.com:idea:


thanx......

 

[Iouri]

adc and dac

**broken link removed**

**broken link removed**

check it out is it what you need?