How to design CMOS D clocked Flip-flop?

How to design CMOS D clocked Flip-flop with CLEAR input?

Hi,

I am looking for a GATE/transistor level design of a D-flip-flop where I would have three inputs, i.e. D, CLK and CLEAR, and two outputs Q and Q'.
I am not a digital guy so don't know much about these Latches/flip-flops....So please help me in this regard.

Regards.

Falstad's animated simulator does not specifically list a D flip-flop made from discrete components.

It provides a link (below) which will open a simulation of a CMOS flip flop made from discrete mosfets. It will run interactively on your computer. (Click Allow to load the Java applet.)

Click the logic inputs which are labeled S and R. Watch the outputs Q and not-Q change.

https://tinyurl.com/d8g2ucc



Beyond this level it is typical for schematics to show flip-flops in the form of abbreviated symbols.

If you want to go to the effort, it should be possible to go through the simulations linked below, and find a way to replace the logic gates with discrete components (each gate being made from several components).

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Falstad's lists a Master-Slave (clocked D) flip-flop . It is constructed from inverters.

https://tinyurl.com/cl57utl

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Master-slave (clocked D) flip-flop constructed from NAND gates:

https://tinyurl.com/cw6mqsv

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Tri-state-inverter-feedback DFFs seem to be the norm.
Have been for at least 30 years (in CMOS). Here's one
from a 1984 standard cell library that is no longer in
production.