How to design an N channel enhancement mosfet?

[long88]

Hi All,

Currently i am doing some design with the use of N channel enhancement mosfet(Farnell order code:1984627).
My purpose was to isolate the input an output circuit by using an N channel mosfet. Please see the attachment.
I really need some help from you guys. Please feel free to share with me so that i can learn. Thank you very much.

 

[barry]

re: Hep with N channel enhancement mosfet design?

You can't do that. It says right in the spec, VGS=4.5 volts. You've got a VGS of zero. (VCC-VCC). Besides, regardless of WHAT voltage you put on the gate, you're going to have VCC-.6 volts on the drain because of the parasitic diode (see, it's right there on the symbol).

I'm not quite sure what you are trying to do, but a MOSFET is not going to 'isolate' anything. Do you have two supplies that you want to switch between? Or do you want to supply your system from either the cap or VCC. It's not clear what your intent is.

 

[long88]

re: Hep with N channel enhancement mosfet design?

Hi Barry,

Sorry , i didn't specific my question clearly. I reorganized my sentence and reattached my question and mechanism. Please have a look.
Thank you very much.



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Hi Barry,

Do you got any better isolation circuit which i can used and work the same purpose?

Thank you very much.

 

[barry]

re: Hep with N channel enhancement mosfet design?

So your "isolate VCC" is not a source, it's just the name of that node? And I don't know what "3V above" means. Still, you can't put VCC on both the source and the gate, you'll never turn the mosfet on, the only way current flows out of the drain is through the parasitic diode.

I THINK (and I could be totally wrong because I'm trying to read your mind) what you REALLY want is to charge the cap and supply VCC to the node Isolate VCC when Vsense is on, and supply voltage from the cap to Isolate VCC when Vsense is low. Is that correct? If that's the case, you're going about this all wrong (besides VCC on the source).

 

[FvM]

re: Hep with N channel enhancement mosfet design?

Besides some confusion about words, barry clarified the basic problem, you need a positive Vgs voltage to turn a N-MOSFET on. If you don't have it, you might think about a P-MOSFET, which can be turnd on with negative Vgs.

 

[long88]

re: Hep with N channel enhancement mosfet design?

Hi Barry,

I THINK (and I could be totally wrong because I'm trying to read your mind) what you REALLY want is to charge the cap and supply VCC to the node Isolate VCC when Vsense is on, and supply voltage from the cap to Isolate VCC when Vsense is low. Is that correct?
Reply: Correct. That is what i was trying to do. If i can' t use mosfet to isolate, can you share me some advise how to isolate the Vcc and Vcharge?

Why i can't supply both Vcc to the gate and source to turn on the mosfet?
What does this sentences "besides VCC on the source" means?

I really appreciate your great help. Thank you very much.

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Hi Barry,

In my circuit, the Vcc will be 3.3v . I hope there is a circuit which i can isolate Vcc and (Isolated Vcc) V charge with no voltage drop between this two node. However, if i use mosfet, there will be a voltage accross the mosfet and my Isolated Vcc will less than 3.3V. My requirement was to obtain voltage 3V or 3V above at the node Vcc isolated .

 

[FvM]

re: Hep with N channel enhancement mosfet design?

Why i can't supply both Vcc to the gate and source to turn on the mosfet?

Because Vgs threshold is a positive quantity for NMOS enhancement transistors. You have to supply e.g. +6V to the gate.

Apart from this problem, power supply switching with MOSFETs can work well, but it's mostly done with P-MOSFETs for positive supply rails.

 

[long88]

re: Hep with N channel enhancement mosfet design?

Hi FvM,

Thank you very much. So it means 3.3V is not good enough to fully turn on the N channel enhancement Mosfet.
I have tested the P channel enhancement Mosfet, the switching work well and there is not much voltage drop accross Vds.
But i can't use the P channel enhancement Mosfet for my application.
When there is a power trip, the voltage at Vcc node will become Zero volt. The P Channel MOSFET will turn on and there is a current flow back from source to drain (Isolated Vcc to Vcc).
I got no way to turn off the MOSFET.

 

[FvM]

re: Hep with N channel enhancement mosfet design?

But i can't use the P channel enhancement Mosfet for my application.

I presume, you just didn't figure out how...

Source and drain must be flipped for a PMOS transistor of course, due to opposite polarity of the substrate diode. The control circuit has to be adapted to the different source connection. In case you want to "isolate" both current polarities, an anti-serial MOSFET pair would be necessary.

 

[long88]

Hi FvM,

Please see the below image. I am not sure what whether my concept was correct.
What is anti-serial MOSFET pair? Am i working in the correct direction? Does mosfet able to isolate voltage between V charge and Vcc?
Thank you for you patience on guiding me. I really quite confuse now.

 

[barry]

You should use a P-channel mosfet. What you've got there in your first drawing is a source follower, the voltage at the source will NOT be VCC, it will be Vcontrol-Vgs. Using a logic-level P-channel mosfet, connect the source to VCC and the drain to your output. Pull the gate to ground to turn the mosfet on.

 

[long88]

Hi Barry and FvM,

Thank you for precious advise. I got another idea to isolate the Vcc and Vcharge. Please have a look on the pic below.



Does this method work ? Thank you very much.

 

[barry]

What? That's a voltage follower. It's not isolating anything. Again. Why won't you use a P-Channel FET? IT'S THE RIGHT WAY TO DO IT!!

 

[long88]

Hi Barry,
Thank you always advice to me although i am very noob in the electronci design.

Yup. This is a voltage follower circuit if the VCC is 3.3V. During power trip, VCC become 0V and the OPAMP will block the current flow back from Vcharge to VCC. Am i right?

I can't use the P channel MOSFET to isolate the VCC and Vcharge. During power trip , VCC become 0V and i not able to generate a signal to turn off the MOSFET. Therefore i can't use the P channel MOSFET　to isolate them.

 

[FvM]

I can't use the P channel MOSFET to isolate the VCC and Vcharge. During power trip , VCC become 0V and i not able to generate a signal to turn off the MOSFET. Therefore i can't use the P channel MOSFET　to isolate them.

Your analysis is still wrong. With a PMOS transistor, source and drain have to be flipped, so the control voltage is applied relative to "Isolate Vcc".

 

[long88]

Hi FvM,

Do you mind to plot me a schematic so i can have better understanding. Thank you very much.

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Hi Barry and FvM,

What wrong with the OPAMP circuit？ I can't use the OPAMP method to isolate Vcc and Vcharge?

 

[FvM]

What wrong with the OPAMP circuit？

Nothing in theory. It's just not suited as a practical supply voltage switch. E.g. how do you power the OP in circuit?

I believe the problem is that you didn't exactly specify the purpose and intended operation of your circuit, e.g. how the gate control signal is generated. Without this information, no reasonable suggestion is possible.

 

[barry]

Hi FvM,

Do you mind to plot me a schematic so i can have better understanding. Thank you very much.

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Hi Barry and FvM,

What wrong with the OPAMP circuit？ I can't use the OPAMP method to isolate Vcc and Vcharge?

I explained how to use a P-channel in post #11

As FvM points out, how are you powering your opamp? Further, do you know what happens when you apply a voltage to the output of an un-powered opamp? Me neither, but my guess is it has nothing to do with "isolation".

 

[long88]

Hi Barry and FvM,

I will use Vcc to power up the OPAMP.

logic-level P-channel mosfet is a single directional mosfet?

 

[barry]

Hi Barry and FvM,

I will use Vcc to power up the OPAMP.

logic-level P-channel mosfet is a single directional mosfet?

And when VCC goes away, what happens to your opamp? I'm not sure what you mean by 'single directional mosfet'. A p-channel mosfet will conduct when the gate is Vgs(threshold)volts lower than the source.