Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to design a start up circuit in bandgap?

Status
Not open for further replies.

mpig09

Full Member level 4
Full Member level 4
Joined
Aug 26, 2005
Messages
232
Helped
8
Reputation
16
Reaction score
2
Trophy points
1,298
Location
Taipei
Visit site
Activity points
2,810
Hi all:

I am design a bandgap circuit, and the operation voltage (AVDD) is 5V ~ 20V.
My structure is cascode current mirror.
The process is High Voltage BCD process.

Each MOS characteristic that in my circuit is :
0<VDS < 20V
0<VGS < 5V

There are other devices in this process:
1. High voltage PMOS:
0<VDS < 25V
0<VGS < 25V
Vth ~ 1.5V
2. High voltage NMOS:
0<VDS < 25V
0<VGS < 25V
Vth ~ 3.5V

There are two methods to start up bandgap:
1. voltage setting (set VA to ground)
==> It is not suit for my design, that the limitation of VGS (0<VGS < 5V)
==> The High voltage PMOS doesn't have good current mirror characteristic,
so I didn't use it for PMOS cascode current mirror.
2. current setting
==>I didn't have any idea.

Could you give me any suggestion for start-up circuit or paper for me to study?

Thanks.
mpig
 

Attachments

  • bg.jpg
    bg.jpg
    36.4 KB · Views: 130

You need a "normally on" current, first. Then you need a
switch that applies it until output is up and stable, then
takes it completely away so as not to bother the core.
That's the tricky bit since many node voltages vary greatly
with process & temp.

While a diode-steered resistor can work, it often is found
to meddle at some corner or fail to boot at the opposite.

In later designs I've tended to use a hard switched hysteretic
control based on the bandgap voltage exceeding some
minimum limit. Where this limit lies, has to do with the
sub-operating-point loop gain, how far out can you be
and still snap-to the desired operating point under all
conditions?

That simple loop is probably fairly low gain.

Given that you are in a BCDMOS process I'd suggest
looking at a completely BJT based PTAT core. Then you
can probably find a lot of simple startup circuit art in
older IC design textbooks (blue binding Gray & Meyer,
etc.). But still beware the curvature or plain messed-up
contribution of a mis-scaled startup bleed.
 

I found it needs a pre-regulator to supply bandgap then add
a start up circuit for bandgap.

I will try it.

mpig
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top