Hello, I am designing a switched capacitor integrator,but I encountered a difficulty in design the switches, it seems that there is current leakage from the source or drain,can someone help me?How can I get a high performance mos switch?
Thanks in advance.
first the ratio of W/L should be optimized, then choose a suitalbe absolute value of W and L. If still couldn't satisfy requirement, use dummy device or adopt bootstraping or bottom-plate sampling technique.
mos switch for Sample/hold need low leakage , simple mos like CD4016
is better than CD4066 ,
but cmos switch CD4066 have low Rds ..
In asic design , you cn use "dummy sw" reduce charge_inject & clock feed_thru
maybe "unless" --> some porfessor said even text book said
add dummy switch can reduce charge_inject
another problem is mos Rds & Vth drop on mos switch
in some volt double circuit like charge pump use pmos for Hi-v input
(nmos vo= vin -vtn) but even though .. vin = 2* vin -v1 ..
I simulation find Vo= 6.16v not 3.3v*2=6.6 still have volt drop
cmos switch I use 20/0.5 * 200 size ..
have anyone ever design charge_pump ASIC , Io=100ma
can you tell me how to design mos switch
u can use a dummy switch or a transmission gate switch to minimize the leakage from source and drain.also for the switch u require the on resistance to be very low so optimize the w/l ratio.clock for dummy switch is somewhat delayed w.r.t. switch
For the analog ic design, you just need to select right topology, then base on the what's clock frequency and signal frequency is, work out a reasonable settling time, to decide the switch W and L, then use a bootstrapping clock for critical switch. Please forget dummy switch, it is not true at some case.
can you give some information about efficiency of clock bootstrapping for (pass-gate) switch and bulk-source forward-biased polarization at 0.12u technology?