frequency comparator flip flop
PLL usually uses PFD (Phase Frequency Detector) to compare frequency and phase differences between 2 clocks .This is simply performed by using 2 D-flip flops each triggered by one of the clocks and D connected to '1' and the outputs of the 2 flip-flops are anded and connected to the asynchronous reset of the 2 flip flops .This circuit would be a good frequency comparator but it is also a phase comparator ,meaning that it would give an output even if the 2 clocks have the same frequency but different phases .
I suggest an alternative method (but I'm not sure if it will work) .Design 2 counters each driven by a different clock (both counters have the same size) .At start of comparison reset both counters ,then when one counter overflows, check the value of both counters ,if both are the same then the clocks are equal to certain accuracy .If not ,then the first one overflowing is of higher frequency and the difference of counters' values can give you the relative frequency difference .
For better accuracy use larger counters but the output will take more cycles to be given .