Re: how to design a CMOS voltage reference circuit?
But my process doesn't provide bipolar transistors
it seems like the bandgap reference circuit always need the bipolar transistor acting as diode, is it true?
Is it possible to implement the bandgap reference circuit only with CMOS transistors?:|
Re: how to design a CMOS voltage reference circuit?
I think that this web can help u http://www.designinganalogchips.com/
u go to this side n than download the book "Designing Analog Chips" try to read it more mayb u can solve ur problem. Good Luck!
Re: how to design a CMOS voltage reference circuit?
katrin said:
But my process doesn't provide bipolar transistors
it seems like the bandgap reference circuit always need the bipolar transistor acting as diode, is it true?
Is it possible to implement the bandgap reference circuit only with CMOS transistors?:|
CMOS transistor worked in the sub-threshold region has the same behavior as the bipolar transistor. maybe you can use it to build a bandgap. there're also some papers on it.
Re: how to design a CMOS voltage reference circuit?
katrin said:
But my process doesn't provide bipolar transistors
it seems like the bandgap reference circuit always need the bipolar transistor acting as diode, is it true?
Is it possible to implement the bandgap reference circuit only with CMOS transistors?:|
I believe the CMOS process provides Diode devices. This diode can be replaced with BJT transistor in which they do the same function. If you are dealing with IBM process, you can look into it, they have explained about the diode characteristic.
Re: how to design a CMOS voltage reference circuit?
Don't worry about it. No-matter what process you used. It can be generated.
If you used CMOS process, it can be generated by using lateral BJT.
If you used BiCMOS process, that's no problem there.
Cause it natural include BJT model.
Re: how to design a CMOS voltage reference circuit?
Every CMOS have P+/NWELL diodes. These are used to generate the kT-Basic-Cell. Most designs using a 8/1 or 15/1 diode array. The issue is that an PMOS input stage opamp is used to regulate the current so that the volatge difference in the kT-Loop is zero. If there is an offset in the PMOS pair it will be seen as voltage variation of the bandgap voltage.
If you use the P+/NWELL as lateral PNP bipolar transistor you will have a low Beta of 10 to 20 or even lower. But that mean that about 0.9 to 0.95 of the emitter current will receive at the P+ collector. That is enough to insert resistors to have a moderate gain of about 5-8. Then the device size of the PMOS input stage could be made much smaller and the bandgap voltage is less process dependend.
The process modelling and extraction in the CAD will possible forbid such circuit. But most processes have thet feature.