How to design a clock recovery module?

[master_picengineer]

Clock recovery

Hi,
I think about designing a Clock recovery module.
How should i proceed ?

 

[plusminus]

Re: Clock recovery

Where do you want to recover your clock from?

Manchester code?

 

[master_picengineer]

Clock recovery

Hi plusminus,
Yes for the first version of the design i will recover the clock from a serial Manchester Coded signal. For the second version, and in the hope of reducing power due to switching activity, the recovery will be from a NRZ coded signal.

Added after 2 hours 50 minutes:

VHDL will be used as specification language. Please teel me how to proceed.

 

[nxtech]

Re: Clock recovery

Your question on how do I proceed tells me that you dont truly understand the basics of Manchester or NRZ encoding. If you did then you would understand how to pull the clock signal from either encoding method.

Take sometime and do some research before you start a project like that.

E

 

[master_picengineer]

Clock recovery

In fact I am new in this domain. That I wanna know is to understant the recovery principle. The thing that i couldn't understand is how to generate the clock from a signal when there we hava a sequece of '1' or '0'. You can consider the worst case obtained in a simple non coded signal.

 

[nxtech]

Re: Clock recovery

The clock is part of the datastream. Go to this link and start reading.

**broken link removed**

E

 

[plusminus]

Re: Clock recovery

The total story is a bit to long to explain but in essence it works like this:

At the transmitter side you multiplex the bitstream data with a clock ( exor ).
At the receiver side you can extract the data and clock by a (D)PLL circuit.

See also: https://www.xilinx.com/bvdocs/appnotes/xapp339.pdf
http://www.ee.iitm.ac.in/~balajis/EE500/Manchester.pdf [/img]

 

[master_picengineer]

Clock recovery

Thank too much nxtech and plusminus.