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how to design a circuit which generate opt which is high for 2 clk cycles and low for

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kannan1

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how to design a circuit which generate output which is high for 2 clock cycles and low for 1 clock cycle repeatedly
 

udhay_cit

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Can you use microcontrollers for that?
 

j_andr

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create a 3-bit barrel-register, initialize it to any of value: 110, 101, 011, use any bit as your clock;

j.a
 

udhay_cit

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So you need like this....

Untitled.png
 
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