Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

how to design a circuit which generate opt which is high for 2 clk cycles and low for

Status
Not open for further replies.

diaz080

Member level 4
Joined
Oct 3, 2012
Messages
72
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,707
how to design a circuit which generate output which is high for 2 clock cycles and low for 1 clock cycle repeatedly
 

udhay_cit

Full Member level 6
Joined
May 16, 2008
Messages
341
Helped
37
Reputation
74
Reaction score
37
Trophy points
1,318
Activity points
3,838
Can you use microcontrollers for that?
 

j_andr

Full Member level 4
Joined
Mar 30, 2008
Messages
208
Helped
59
Reputation
118
Reaction score
37
Trophy points
1,308
Location
europe
Activity points
2,491
create a 3-bit barrel-register, initialize it to any of value: 110, 101, 011, use any bit as your clock;

j.a
 

udhay_cit

Full Member level 6
Joined
May 16, 2008
Messages
341
Helped
37
Reputation
74
Reaction score
37
Trophy points
1,318
Activity points
3,838
So you need like this....

Untitled.png
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top