How to design a 64bit adder in VHDL?

[bassem11]

adder

i need to desing a adders 64 bit in VHDL
what is the best way ti desing and which adder do you think i need to desing according to area and time

 

[devrimaksin]

adder

If you are using VHDL, you dont have a lot of choice
after all what you will write is
out=in1+in2

Now, the difference comes to play when you synthesize it, and the result depends on
1. Synthesis library that you have
2. Synthesizer that you have
3. The constraint the you pose to synthesizer to do the job

If you are trying to design IEEE 64 bit adder (like in ALU) kind a stuf, you should do it full-custom

 

[bassem11]

Re: adder

i need to desing 128 bit and for me this is the first time i use this languge
and i need to desing it according XLinx Virtex2 xc2v500

 

[craftfox]

adder

your can design it at gate level. i.e. use the "or" logic\"xor"logic\"and" logic. I completed one 64-bits signed adder last month using the verilog. I think it's easy to transfer it into VHDL code if you like to.
ps you can not find the existing one on the internet. so read the article carefully and depend on yourself.

 

[Big Boy]

Re: adder

Just make sure of the following substility...

- If you add two 64 bits number, you get a 65 bits result (or a 64-bits result plus a carry output bit).

- You can have an adder that take into account a carry bit at input too. The same rule as above apply with and without input carry bit.

- Take into account if you add signed or unsigned numbers.