How to delay the output? My code does not work

how to delay the output?

Hi all,

My input is of 10Mhz (100ns). Clock of the CPLD is 80MHz.
There is 5-bit Delay selection line which selects the input to be delayed by number of clock cycles.
e.g., 00101 delays output by 5 clock cycles 12.5*5 = 62.5ns
but my code does not work after 00011 selection. Please anybody help me out.
Here is my code.



library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fiber_splitter is
port(clk : in std_logic;
inp_wave : in std_logic;
delay_sel : in std_logic_vector(4 downto 0);
out_wave : out std_logic);
end fiber_splitter;

architecture Behavioral of fiber_splitter is

begin
process(clk)
begin
--if(clk'event and clk = '1') then
case delay_sel is
when "00000" => out_wave <= inp_wave;
when "00001" => out_wave <= inp_wave after 12.5ps;
when "00010" => out_wave <= inp_wave after 25.0ps;
when "00011" => out_wave <= inp_wave after 37.5ps;
when "00100" => out_wave <= inp_wave after 50.0ps;
when "00101" => out_wave <= inp_wave after 62.5ps;
when "00110" => out_wave <= inp_wave after 75.0ps;
when "00111" => out_wave <= inp_wave after 87.5ps;
when "01000" => out_wave <= inp_wave after 100.0ps;
when "01001" => out_wave <= inp_wave after 112.5ps;
when "01010" => out_wave <= inp_wave after 125.0ps;
when "01011" => out_wave <= inp_wave after 137.5ps;
when "01100" => out_wave <= inp_wave after 150.0ps;
when "01101" => out_wave <= inp_wave after 162.5ps;
when "01110" => out_wave <= inp_wave after 175.0ps;
when "01111" => out_wave <= inp_wave after 187.5ps;
when "10000" => out_wave <= inp_wave after 200.0ps;
when others => null;
end case;
--end if;
end process;
end Behavioral;


Thanks in advance

Re: how to delay the output?

As far as I know the 'after' is for simulation only, and can't be synthesized.
So, you have to create a 63-bit shift register, and use a multiplexer to select the appropriate output.

Something like this 'code', which is not checked at all and only shows the basics: