In my design, I have a problem, because of the hold time requiement, I have to
delay the Address bus for about 2 or 3ns compared to the clock, can anyone give
me some suggestion about this problem? I dont think it's a good idea to delay the
bus? but I have no good idea?
thanks
anderson
thanks for your kind
the question is that if i add delay, I need to add for every bit of the Address bus
I use the delay cell in the lib, when I do synthesis, I use don't touch command for
these delay cells,but I don't think is a good idea,any other good choice?
thanks[/quote]
the following picture, clk is aligned with Address, the hold requirement is 0.5ns
so I decided to delay the Address to Address1, which meet my need.
* Make the clock early to the addressregisters, that way you can save in adding more buffers. If you dont want to disturb clock path, then the option is to use delay cells to delay the data path.