I really dont know, it depends on how much delay you want. and i dont think the transmission line on the chip will provide too much delay by itself.
if you put the transimission line off chip, it is another story.
otherwise, i think using inductor would be more area effcient than transmission line.
and for cascaded single stage DA, just one inductor for one stage. and if you want more delay, put more stages. and the delay is the result of using both inductor and capacitor.
Could the following help you....
IEEE,JSSC,NOV-2005,A monolithic Digitally controlled delay elemnt, M Maymandi...
it says in 0.18umCMOS, from 2ps above delay resolution...