array in vhdl
The Array declaration type is of the following type:
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TYPE SAMPE_main IS ARRAY (1 to 10) OF INTEGER;
CONSTANT SAMPLE : SAMPLE_main := (1,2,3,4,5,6,7,8,9,10);
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In your design,
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PROCESS(CLK) THEN
VARIABLE i : INTEGER RANGE 0 TO 10;
BEGIN
IF RISING_EDGE(CLK) THEN
i:=i+1;
IF(i<10) THEN
OUTPUT <= SAMPLE(i);
ELSE
OUTPUT <= SAMPLE(i);
i:=0;
END IF;
END IF;
END PROCESS;
For each clock, every array index value will be accesed and it's being looped. Hope this helps..