How to decrease rise and fall time for inverter

[wzhlove2003]

I designed an inverter in TSMC 0.18um process. NMOS is 900nm/200nm X2. it can contain 2 contacts. and PMOS is 2.7um/200nm X2. So the width of PMOS is three time than NMOS. this inverter drive 10fF capacitor and an another inverter. .

Rise time and fall time are equal and about 48ps.

So How can i decrease rise and fall time? I'm trying to achieve 30ps or below.

Thank you
JT

 

[vlsi_whiz]

You could try changing the load capacitance to a lower value so that it charges and discharges faster, or change the W/L ratios of the PMOS and NMOS for the new timing.