How to declare bidirectional bus in verilog testbench?

[thaolam]

Hi,

I am creating testbench for SRAM.

When WREN_N=0 && BFRD=0 && OE=0, SRAM will do write operation with input Data is D[7:0].

When WREN_N=1 && BFRD=1 && OE=1, SRAM will do read operation with output Data is D[7:0].

WREN_N: write enable pin, active at low
BFRD: read enable pin, active at high
OE: output enable, active at high, using is read mode.

I am declaring D as the following (referring the similar threads):

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Code Verilog - [expand]
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module s65fh_sp528x8x8_test ;
        supply0 gnd_1;
        supply1 vdd;
        wire [7:0] D;
        reg [0:9] BA;
        reg BFRD, RY_EN, SLOWRD_EN, POR_N, OE, WREN_N;
        reg clk;
        integer i=0;
        reg [0:23] ivector,temp;
        reg [0:23] wvector[0:528] ;
        reg [0:23] rvector[0:528] ;
 
s65fh_sp528x8x8 s65fh_sp528x8x8 (.BFRD(BFRD),.WREN_N(WREN_N),.RY_EN(RY_EN),.SLOWRD_EN(SLOWRD_EN),.OE(OE),.POR_N(POR_N),.D(D),.BA(BA),.gnd_1(gnd_1),.vdd(vdd));
initial begin
        wvector[0] = {1'b0,1'b0,1'b1,1'b0,1'b0,1'b1,8'b00000000,10'b0000000000};
        wvector[1] = {1'b0,1'b0,1'b1,1'b0,1'b0,1'b1,8'b00000001,10'b1000000000};
        wvector[2] = {1'b0,1'b0,1'b1,1'b0,1'b0,1'b1,8'b00000010,10'b0100000000};
        wvector[3] = {1'b0,1'b0,1'b1,1'b0,1'b0,1'b1,8'b00000011,10'b1100000000};
        wvector[4] = {1'b0,1'b0,1'b1,1'b0,1'b0,1'b1,8'b00000100,10'b0010000000};
        wvector[5] = {1'b0,1'b0,1'b1,1'b0,1'b0,1'b1,8'b00000101,10'b1010000000};
        ....
end
 
always@(posedge clk)
 temp=ivector;
 
//bidirectional data
 
        assign D=(OE == 0 && WREN_N == 0 && BFRD == 0) ? temp[6:13] : 8'bz ;
....
end
endmodule

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However, I am getting failed in result. By reviewing waveform and netlist, I am seeing that the D, node after D input buffer for write, and node before D output buffer for read have the same logic. I wonder my declaration of bidirectional D is right or not? Please help.

 

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