In your example you have unique parameter names which must be assigned and referenced individually. What's the problem with having some unused parameters in your module? It's however possible to define parameter arrays with variable bounds, e.g.
Code Verilog - [expand] |
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| parameter A = 2,
parameter B = 5,
parameter real a[1:A] = '{1.52,2.34e5},
parameter integer b[1:B] = '{1,2,3,4,5}, |
Thanks for the answer FvM.
What's the problem with having some unused parameters in your module?
I gave a simplified example to make my point, but in my real code, when I change NUMBER_OF_A, NUMBER_OF_B, and NUMBER_OF_C, it generates additional HW which uses the parameters generated (in this example, A1, B1, B2...etc.). If I generate unused parameters, it will reflect with additional real HW. In my case, this is bad because I am trying to find a good relation between parameters which generate an optimized HW, meaning additional parameter reflects in additional logic and decreased final frequency.
Please note hat my parameters will not be static, I really want to change it a lot to generate different scenarios. For example, if I changed NUMBER_OF_B to 4, I would like to have the parameters C1 shifted in values as well (B4 = 8'd4 and C1 starting in 8'd5 for example). So, in your example, I do not see how to change the number of vectors and its value dynamically (or is it possible)?
Lastly, to make thinks "simpler", I am using ISE 14.7, so this is Verilog and not System Verilog :-|
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Did you try compiler directives? You can get it done with
but it might look ugly.
I do not have problem in using `define but I still do not see how this might work. Could you please give an example?
Is it possible to used `define coupled with generate? I think it is not possible to generate multiple `define this way, but I am really not sure.