Re: How to decide the value of sample capacitor in pipelineA
Hi,
Below is the calculation process: for 8bit pipelineADC, ideal SNR=6.02*N+1.76
=49.92db, where N=8. I assume that 1db degradation of SNR is designed for the error budget, then SNR=48.92db. We know that the ideal SNR is comes from quantify noise, 1db degradation is deduced when the thermal noise is considered in SNR calculation.
The sampling and feedback capacitor sizes are determined by KT/C noise constrains. A fundanmental noise source present in ADC is thermal noise, and the magnitude of this noise is a function of the sampling capacitor size(σ²≈KT/C)
SNR=-10log[(2/3)*(1/2Λ2N)+2*Vnoise²/Vref²) (1)
Where the 1st item is ideal SNR, the 2nd is SNR deduced by thermal noise, Vnoise² is the total thermal noise, Vref is half of the full-scale voltage, that is 1/2*(Voutp-Voutn).
According to one master thesis(sha stage+6*1.5bit stage+2bit flash stage=8bit):
Vnoise²≈2.67KT/fC (2)
Where f is the feedback factor. Then set SNR=48.92 and f=1/3(for 1.5b stage pipeline f is between 0 and 0.5, here we assume its value is 1/3, inter-stage gain is 2, and Cs=Cf)). We know
C=25fF.
I think this value is already meet the SNR requirement, why do we select a ~0.5pf level capacitor? Big capacitor means more power consumption and lower
speed.
Thx for your all attention, your help is my hope.