How to decide the value of sample capacitor in pipelineADC?

[philipwang]

Hi,
Sample capacitor value is decided by SNR requirement of the pipelineADC.
For 8bit pipelineADC, the ideal SNR is 49.96db, 1db degradation of SNR is designed for in the error budget, then 25fF capacitor is deduced. But in many actual design the sample capacitor is ~0.5pF. My problem is: why we select such level a capacitor as the design value instead of 25fF? Maybe the parasitic capacitor and capacitor mismatch should be considered?
Thx for your help!

 

[extraord]

Re: How to decide the value of sample capacitor in pipelineA

25fF cap is too small, even parasitic cap is much larger than this.
so the accuracy is difficult to achieve.

 

[opamp741]

Re: How to decide the value of sample capacitor in pipelineA

Cap value is not anywhere close to practical ones..post ur calculations.. and tell all the assumptions u made..in practical pipelined ADCs we do scaling of the sampling caps and 1st stage sampling cap generaly comes in the range of 200f-400f..KT/C decides the cap value for last stage..

 

[philipwang]

Re: How to decide the value of sample capacitor in pipelineA

Hi,
Below is the calculation process: for 8bit pipelineADC, ideal SNR=6.02*N+1.76
=49.92db, where N=8. I assume that 1db degradation of SNR is designed for the error budget, then SNR=48.92db. We know that the ideal SNR is comes from quantify noise, 1db degradation is deduced when the thermal noise is considered in SNR calculation.
The sampling and feedback capacitor sizes are determined by KT/C noise constrains. A fundanmental noise source present in ADC is thermal noise, and the magnitude of this noise is a function of the sampling capacitor size(σ²≈KT/C)
SNR=-10log[(2/3)*(1/2Λ2N)+2*Vnoise²/Vref²) (1)
Where the 1st item is ideal SNR, the 2nd is SNR deduced by thermal noise, Vnoise² is the total thermal noise, Vref is half of the full-scale voltage, that is 1/2*(Voutp-Voutn).
According to one master thesis(sha stage+6*1.5bit stage+2bit flash stage=8bit):
Vnoise²≈2.67KT/fC (2)
Where f is the feedback factor. Then set SNR=48.92 and f=1/3(for 1.5b stage pipeline f is between 0 and 0.5, here we assume its value is 1/3, inter-stage gain is 2, and Cs=Cf)). We know
C=25fF.
I think this value is already meet the SNR requirement, why do we select a ~0.5pf level capacitor? Big capacitor means more power consumption and lower
speed.
Thx for your all attention, your help is my hope.

 

[Btrend]

Re: How to decide the value of sample capacitor in pipelineA

1. in my opinion, if u can control the parasitic induced from all layers (substrate, poly, Metals), then ur assumption may be worked. But in real world, it is hard to match all the parasitic capacitors.
2. for 8bit resolution AD, the S/H should be also 8bit resolution.
assume Ci : sampling cap. Cf : feedback cap. Vo: output of S/H, Vi: input of S/H
===> (Vo-Vi)=Vi*(Ci/Cf)-Vi= Vi(Ci-Cf)/Cf ---- (a)
eq. (a) must be less than 1LSB=FS/256

3. assume FS=1V, Vi=1V and Cf=Ci-ΔC
===> (Ci-Cf)/Cf = (ΔC)/(Ci-ΔC) < 1/256
===> ΔC < Ci/257
===> ΔC < 25f/257= 0.097fF -----(b)
4. As stated in (1), if ur un-match cap. is lower than (b) then Ci=25fF is feasible.
5. u can check the parasitics after layout. and run post-sim to verify this.

 

[philipwang]

Re: How to decide the value of sample capacitor in pipelineA

That is to say, if we select the Ci(sample capacitor) 200fF-400fF, the reason mainly comes from the capacitor mismatch consideration. For 25fF capacitor, is 0.1fF mismatch reasinable?

 

[Btrend]

Re: How to decide the value of sample capacitor in pipelineA

1. usually there are switches in pipeline AD, and these switches contribute parasitics in a different way when ur S/H is in Sample and Hold state.
2. u can extract ur layout to see how much difficult it is to achieve 0.1fF matching.
3. there is a technique to reduce this matching barrier, it is capacitor averaging, u can search it in JSSC.