Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to decide the bias current in designing CML latch ,

Status
Not open for further replies.

pavan5720

Newbie level 5
Newbie level 5
Joined
Aug 27, 2012
Messages
9
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Visit site
Activity points
1,326
I am Desigining a CML d LATCH IN 0.18um technology Cadence Virtuoso , how to decide the bias current and the regenrative time
 

Hi, the bias currents are generally decided by the regenerative time. The differential current ~ gmrp --> reduce the regenerative time incr bias currents & during small signal differential regenerative voltage -->gm*rp*t/cp
 

If say the swing is 0.4v , capacitance c is 0.5p , let the regenrative time is 0.05n second , as Q=i*t, Q=c*Vswing, so I=C*vSwing/Treg , I tried doing this but regeneration is not working , corect me if i am wrong
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top