Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Size of the FIFO basically refers to the amount of data available at a given time. In asynchronous FIFO this depends on both read and write clock domain frequencies and number of data written and read (data rate). Data rate can vary depending on the two clock domain operation and requirement (and of course frequency!). The worst case condition is the maximum data rate difference between read and write clock. This can happen when data rate of writing operation is maximum and for read operation data rate is minimum.
Let fwrite--> be the frequency of write clock domain
Fread--> be the frequency of read clock domain.
Bmax--> burst of data written or maximum number of data bytes can be written
Bwrite--> number of bytes that is written per clock cycle
Bread-->number of bytes that is read per clock cycle
Then FIFO size can be given by,
If number of bytes read or written per clock cycle is one then we have,
In our case, fwrite=10 MHz
Let Bmax=2 then Fsize=2-[(2*2.5)/10] =2-0.5=1.5~2
If Bmax=5, then Fsize=5-[(5*2.5)/10]=5-1.25=3.75~4.