I want to test memories for manufacturing defects. For that I am using MBIST Architect tool from mentor graphics which will insert controller and do the testing. But what my doubt is if I have lot of memories of different types(single port,dual port and two port register file) and of different sizes( data and address), How the tool will decide on the number of bist controllers to test all the memories?
you can specify list of the memories to be present in one bist wrapper file in your do file.
like
add mem model rf1_256x131 -bypass user_mem_bypass_name
add mem model rf1_256x15 -bypass user_mem_bypass_name1
add mem model rf1_256x179 -bypass user_mem_bypass_name2
add mem model rf1_256x15 -bypass user_mem_bypass_name3
make sure you specify the corresponding atpg model for each memory using load_library.
Then tool generate wrapper files and gives separate handle to each memory.
For all the memories you mentioned in thread how many bist controllers are needed and on what basis the tool will decide on the no of bist controllers?
tool will generate one bist.v and bist_con.v
bist.v contains bypass modules for each memory
bist_con.v is the one you instantiate in your design .
bist_con.v provides separate ports for each memory.
bist.v will be instantiated inside bist_con.v