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I think it's more about the ambient noise sources, like
power supply ripple, local clocks, etc. You would like
the LDO to have a decent high frequency PSRR to tamp
these down at the VCO, where they become phase noise /
jitter contributors. At 100MHz+, you really have to count
on decoupling caps rather than active circuitry to roll
off self-generated "noise".
The topic is IC design. So you can most likely not rely on bypass caps.
Utilizing a voltage regulator for VCO PS interference suppression is a realistic scenario. It has considerably improved
the PLL performance of recent FPGA designs, e.g. Altera Cyclone III. Of course, there can't be external bypass caps at
the regulator output.