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how to debug pattern mismatch during simulation of ATPG pattern

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Ranjit Kumar Rawani

Newbie level 3
Aug 28, 2015
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Hello All,

I am a beginner in DFT field so can anyone elaborate in detail steps to hoe to debug a pattern mismatch during ATPG simulation.
How can I verify that my generated ATPG are correct. In one word plz help me out with the steps of pattern simulation for my inserted DFT to verify my scan architecture.


After you have generated patterns for your design, all you need to do to is pattern simulation to verify your patterns.

Now,answering your first question,
For debugging output mismatch error you need to read "TEST PATTERN VALIDATION" by Synopsis user-guide.
In that you'll find there are six types of output miscompare messages can be present.i.e. Signal XYZ expected to be 1 was X.You need to read this first to debug your simulation failure.

Answer to second question,
Step-1.Create a testbench file(.v file) by using ATPG tool. If you're using TetraMAX ,then write out testbench using write_testbench command.

Step-2.Point the stil(pattern) file which you have already generated into the testbench file to help understanding testbench file which patterns you want to simulate.

Step-3.Don't forget to include your netlist while doing simulation.

Step-4.For simulation tool there are many available,mostly i prefer vcs tool.Take whichever simulation tool you want and start the simulation.

Cheers!! :)

Please do correct me if anything is wrong.
Thanks Shalin for the reply !!

Please elaborate in detail/steps the debug part if I got any miscompare while doing pattern simulation for my inserted DFT. where and why we are using zero-time simulation ?


As per my knowledge, most possible reason for output miscompare could be due to the design consructs that are not matching with application of STIL data.While doing simulation, I have faced this miscompare errors many often, and it was because of the constraints on clock(In my case) which was mismatching with the STIL data. For that i need to edit my spf file.

So,if you are talking about steps for solving them:

Step1. Try to debug which pin/port is having miscompare and which pattern causes the failure.

Step2. Use waveform viewer tools(i.e Verdi,etc) to easily debug the failure. Add clocks in waveform. Try to find the root cause of having miscompare value(expected to be 1 was 0) on that particular pin.

Step3. Check your constraints file. In waveform,see that the output at particular pin is according to the constraints or not.Check why wrong value is coming at that pin.

Step3. Do necessary changes in the SPF file accordingly.

Step4.Also need to know which kind of simulation you are running. serial or parallel. Check that ATPG have generated serial testbench by using write_testbench -serial/parallel command. Also check that your simulation tool is also running the simulation in that particular mode.

Please do correct me if i am wrong.


how do I decide to use either parallel or serial simulation? when and where we use serial/parallel simulation ? Suppose my design have both hold and setup violation issue on different flops, then how would I fix these violation by modifying the spf file or there is other way to fix this mis-compare.

Just to clarify, I also have never head of serial/parallel setting for a simulator. May the OP in #4 plz clarify on this?
What he possibly means is feeding the test-patters in a serial/parallel manner. That seems ok, as it can be fixed in the nature of the TB used.

Suppose my design have both hold and setup violation issue on different flops, then how would I fix these violation by modifying the spf file or there is other way to fix this mis-compare
I don't think a test engineer fixes Setup/Hold violations. Typically Setup violations are fixed by design engineers before the PnR stage. Layout engineers later fixes any Hold violations.
Now since you are working/testing a DFT inserted netlist (I assume) so you might work in conjunction with your colleague/s who has/have done the STA.

I had worked for a few months only on ATPG based memory testing. The test-patterns were fed to the post-layout netlist and then the simulations were carried out. So I didn't worry about timing violations.

Regarding your other question on how to debug when pattern mismatches occur:
Well from the waveform viewer you already know at what time instance and for what signal the expect verses the actual values are failing. One way could be to open this signal/signals in the schematic viewer and keep tracing it backwards to the point where its change occurs. In the path you might detect an anomaly which you can then further investigate.
Last edited:

Hi Ranjit,

As dpaul mentioned, Setup/Hold violations are fixed by design engineers,i don't think you need to care about it as we are doing pattern simulation without timing check.

If you are talking about serial/parallel simulation then, let me take you in some deep,

In serial simulation pattern is shfited in to FFs in scan chain through scan-ports.So, more the no. of FFs more time it will take to shift in the pattern.Note that,here, simulator will apply patterns at scan-ports.

In parallel simulation values that should have actually reached the D input of FFs in a scan-chain by shifting through scan-inputs are directly forced at the D input of FFs by simulator.So here, simulator will save time to load-unload the patterns as it is directly forcing patterns at D input of flops.

So, as parallel simulation reduces the time for shifting the pattern you can easily decide which mode to use.
Use parallel simulation when you want to reduce the simulation time.

Cheers.!!! :)
Thanks Shalin,

when and where we are using parallel and serial simulation? Sometimes simulation passed in parallel but failed in serial or vice-versa, please help me out why this happened and how I will correct this type of issues.

According to me,when you are running simulation for design in standard mode(Non-compression mode),you may run whichever(serial/parallel) simulation you want to according to your total simulation timeline.

Till now, i came to know that when we are using compression mode, simulation in parallel mode would likely to fail. So we need to do serial simulation when we have compressed patterns. I am still finding a proper and perfect answer that why it's failing.
Let me wait for some dft experts to give proper answer.

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