how to deal with test SE pin in scan mode when do sta?

[honeyxyb]

how to deal with test SE pin in scan mode when do sta?

 

[horzonbluz]

set_case_analysis 0 TEST_SE
set_case_analysis 0 TEST_MODE

 

[dddain_bramage]

> how to deal with test SE pin in scan mode when do sta?

In scan-mode, are you simulating a "load/unload" or a "capture" cycle? Depending on your DFT-insertion tool/methods, there may be timing differences between the capture and load/unload cycles, so it's best to analyze them separately.

For example,

# CTE (Cadence Common Timing Engine) script -- for engineers who believe
# Synopsys ptsh/dcsh constraints shouldn't rule the world...

# TEST_SE = 'scan-enable' control (1==SCAN, 0==functional-mode)
# TEST_MODE = 'scan-mode' (or test-hold) control (1==ATPG-mode is active)
# TEST_MODE controls clock-muxes and other circuit strctures,
# TEST_MODE==1 puts the ASIC into 'external test-compatible'
# operation
#
# (scan-style is a 'multiplexed' flipflop)

#
# SETUP ( set_operating_conditions, set_clock_propagation, etc.)
#

# 1) Analyze the SCAN "load/unload" cycle
# The unload/load cycle lets the scan-chains shift-data serially
# through the ASIC.

set_constant_for_timing 1 [find -ports TEST_SE]; #
set_constant_for_timing 1 [find -ports TEST_MODE];#

report_timing ...; # do your analysis!

# 2) Analyze the SCAN "capture" cycle
# The unload/load cycle lets the scan-chains shift-data serially
# through the ASIC.

set_constant_for_timing 0 [find -ports TEST_SE]; #
set_constant_for_timing 1 [find -ports TEST_MODE];#

report_timing ...; # do your analysis!


(If you are using Primetime, replace 'set_constant_for_timing' -> 'set_case_analysis')