How to deal with simulation with too many pins?

[william_luo]

Hi everyone,

I have a question when I want to simulate a simple adder by cadence virtuoso. I've designed a 64-bit adder and would like to make a simulation. But it seems too boring when I do so because there are almost 200 pins. That is to say if I just use vpulse (NCSU_Analog_Parts -> Voltage_Sources -> vpulse) in this process, I need more than 100 voltage sources in my design that will be boring and time consuming. Are there some other kind of sources that can be used in this situation or some other method?

Thanks a lot!8-O

 

[sarge]

Hi,

I don't have much experience in such things, but maybe it'll be less boring if you try to use Stumuli option instead voltage sources, or (the best way I think) you have to create Verilog-A block just for tests.

 

[william_luo]

I will try the stimuli option and the verilog-A. Thanks for your help.