How to deal with on chip memory timing?

[fpganewb]

I want to make a fsm on an altera FPGA which uses on-chip memory.
I want to take an input, get data from memory based on input, use that data in the next cycle.
What is a good way to write verilog code for this while keeping timing in mind?

 

[rberek]

Well, the on-chip RAM is synchronous and so is the circuitry you will design to access it. Therefore your main concern is knowing in which clock cycle your output data is valid and using it at that time. When the output data is available varies based on whether or not you register the outputs and what memory implementation you chose from the Megacore tool, or, inferred from the RTL you wrote. If you are generating RAM cores using Altera tools., then the datasheet will explain the memory timing. If you wrote RTL to infer a memory, then you already know when your output data is valid asit is your own design.

r.b.