How to deal with multiple clock frequencies in my Design

[bh_letters]

Hi,

What are the options to deal with multiple clock frequencies in my design? Say, I receive data at a perticular frequency, I need to process the data and send it to an output device operating at different clock frequency. I guess one way to do it is by using FIFO. What are the other options?

Thanks

 

[revolt]

Look at:

https://www.altera.com/literature/hb/qts/qts_qii54003.pdf

Clock Domain Crossing

or

**broken link removed**

 

[adap]

You can use double flip-flops.
The received data is input to a flip-flop. The output of this flip-flop is the input of a second flip-flop. The output of the second flip-flop is the output data you sample.
The first flip-flop has the first clock frequency and the second flip-flop the other clock frequency.

 

[phoenixfeng]

You can use double flip-flops.
The received data is input to a flip-flop. The output of this flip-flop is the input of a second flip-flop. The output of the second flip-flop is the output data you sample.
The first flip-flop has the first clock frequency and the second flip-flop the other clock frequency.

can this really work?
what if the first clock of FF is faster than the second clock of FF?

 

[zape]

If you want to transfer data between clock domains, do not doubt, a FIFO is your solution.
If you need to communicate p.e. a fast clock FSM with a slow clock FSM, the signals must be active for more than one period.

 

[jadyjerry]

Double-Port RAM is also OK!