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How to deal with high-fanout nets using DC

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Newbie level 4
Feb 17, 2002
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For clock nets, we use layout tools to generate clock tree. How about other high-fanout nets such as "reset" nets?

high fanout

You may use "set_dont_touch_network" command for both reset and clock signals in your design.

high fanout net


I mean we should generate a "reset tree " using layout tools or just use DC to synthesize those high-fanout nets except clock signal.

asynchronous reset tree synthesis

Hi, I usually generate the reset tree during layout. so, as jazz_roa suggested, I set_dont_touch on clock and reset.

high fanout nets

The set_dont_touch_network command is intended primarily for clock circuitry. Placing a dont_touch_network on a clock object prevents compile from modifying the clock buffer network.
You may use "set_dont_touch_network" command for reset design.
Ramo :lol: :lol: :lol:

high-fanout nets

Leave this to back-end tool is prefer. Otherwise u can use DC
balance_tree . But u have no location and real wire load data.
So this may happen to vilatoe some timing issue if u care about it.
I found current library from Main foundry could create large fan-out
if u just constraint the trasistion time in their default value (said 2ns).
I wonder if this is a real design rule or just a estimate design rule based on foundry engineer's experience.

high-fanout net + synthesis

Actually it will depend how many cells the reset signal is gonig to.
If you want to let the synospys DC to add buffers for reset signal,
use set_max_fanout 20 your_design, something like that. And
use balance_buffer command to insert reset buffer after synthesis.

That's the approach I used in my past design.

high fanout net report

I always use "set_dont_touch_network" and let the vendor make
the reset tree. The way you use the reset in your design will impact
the reset implementation. The main use of the reset is prevend "X"
during simulation.
I thing the best way to implement the reset logic is to use a global
asynchronous reset (RESET PIN) going to all top level modules in
your design. Then, each module generate a local synchroneous reset
in his own clock domain. Use double-sampling and have the async.
reset connected the async set or clear pin of the two flip-flop. Connect
the D pin to HI or LO (According to the polarity of the reset you need)
and connect the Clock to the clock domain for which the reset is to be used.

typical fanout for clock synthesis

The clock-tree synthesis/optimize tool "clockwise" from Celestry can synthsize not only clock-tree but also high fanout net (ie. Reset net).

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