Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

How to deal with high-fanout nets using DC

Status
Not open for further replies.

magicball

Newbie level 4
Joined
Feb 17, 2002
Messages
7
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
64
set_dont_touch_network

For clock nets, we use layout tools to generate clock tree. How about other high-fanout nets such as "reset" nets?
 

jazz_roa

Junior Member level 2
Joined
Jan 21, 2002
Messages
20
Helped
3
Reputation
6
Reaction score
2
Trophy points
1,283
Activity points
90
high fanout

Magicball,
You may use "set_dont_touch_network" command for both reset and clock signals in your design.
 

magicball

Newbie level 4
Joined
Feb 17, 2002
Messages
7
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
64
high fanout net

jazz_roa:

I mean we should generate a "reset tree " using layout tools or just use DC to synthesize those high-fanout nets except clock signal.
 

ultraunix

Junior Member level 1
Joined
Feb 18, 2002
Messages
15
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
60
asynchronous reset tree synthesis

Hi, I usually generate the reset tree during layout. so, as jazz_roa suggested, I set_dont_touch on clock and reset.
 

ramo

Newbie level 6
Joined
Jan 14, 2002
Messages
12
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
rom
Activity points
95
high fanout nets

The set_dont_touch_network command is intended primarily for clock circuitry. Placing a dont_touch_network on a clock object prevents compile from modifying the clock buffer network.
You may use "set_dont_touch_network" command for reset design.
Ramo :lol: :lol: :lol:
 

Nobody

Full Member level 3
Joined
Oct 4, 2001
Messages
165
Helped
9
Reputation
16
Reaction score
7
Trophy points
1,298
Location
Formosa
Activity points
1,593
high-fanout nets

Leave this to back-end tool is prefer. Otherwise u can use DC
balance_tree . But u have no location and real wire load data.
So this may happen to vilatoe some timing issue if u care about it.
I found current library from Main foundry could create large fan-out
if u just constraint the trasistion time in their default value (said 2ns).
I wonder if this is a real design rule or just a estimate design rule based on foundry engineer's experience.
 

SVTONY

Member level 1
Joined
Apr 10, 2002
Messages
36
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
186
high-fanout net + synthesis

Actually it will depend how many cells the reset signal is gonig to.
If you want to let the synospys DC to add buffers for reset signal,
use set_max_fanout 20 your_design, something like that. And
use balance_buffer command to insert reset buffer after synthesis.

That's the approach I used in my past design.
 

shell3

Member level 1
Joined
Mar 28, 2002
Messages
35
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
303
high fanout net report

I always use "set_dont_touch_network" and let the vendor make
the reset tree. The way you use the reset in your design will impact
the reset implementation. The main use of the reset is prevend "X"
during simulation.
I thing the best way to implement the reset logic is to use a global
asynchronous reset (RESET PIN) going to all top level modules in
your design. Then, each module generate a local synchroneous reset
in his own clock domain. Use double-sampling and have the async.
reset connected the async set or clear pin of the two flip-flop. Connect
the D pin to HI or LO (According to the polarity of the reset you need)
and connect the Clock to the clock domain for which the reset is to be used.
 

S0933263236

Junior Member level 1
Joined
Jul 20, 2002
Messages
17
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
Taiwan
Activity points
78
typical fanout for clock synthesis

The clock-tree synthesis/optimize tool "clockwise" from Celestry can synthsize not only clock-tree but also high fanout net (ie. Reset net).
:D
 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top